Turning to FIG. 1, an example of a system 100 that employs a buck converter 102 in conjunction with an LDO 104 (which provides power from a battery BAT to a powered circuit 106) can be seen. As shown, the buck converter 102 is generally comprised of a plant (which is generally a driver circuit 110, transistors Q1 and Q2, an inductor L, and a capacitor C1) and a controller (which is generally an error amplifier 112, voltage source 114, a pulse width modulator or PWM 108, and a voltage divider R1/R2), and the LDO 104 is generally comprised of an amplifier 116, a transistor Q3, a voltage source 118, and a capacitor C2. In this example, voltage source 114 provides a reference voltage VDCREF to error amplifier 112 such that voltage VOUT (which is generated by buck converter 102 from battery BAT) is greater than reference voltage VLDOREF (by, for example 200-300 mV) in order to decrease the power loss in LDO 104 (which is proportional to its dropout).
In order to save energy, LDO 104 can be disabled (i.e., high impedance output) when high noise can be tolerated, and voltage VDD can be set by a secondary power source (i.e., shorted to ground or left floating). Without a load, buck converter 102 can consume very small amount of current (i.e., down to about 50 nA) and does not have to be turned off. When LDO 104 is re-enabled (during startup), LDO 104 begins charging capacitor C2 to a desired level. Under these circumstances, the output current from LDO 104 can be set very high (which is limited set by the size of transistor Q3 and additional current-limiting circuitry inside, if any), but charging of capacitor C2 is typically limited by the maximum output current of the buck converter 102 (i.e., size of inductor L and transistors Q1 and Q2).
Turning to FIG. 2, a diagram depicting an example of voltage VDD during the startup or re-enabling of LDO 104 can be seen. As shown in this example, when LDO 104 is “off” prior to time T1, voltage VDD is approximately at ground. Then at time T1, the enable signal EN is asserted to enable LDO 104, and capacitor C2 is charged until time T4, when it reaches reference voltage REF1. This delay (due to the charging of capacitor C2) can be quite lengthy, so there is a need for an improved power management circuit.
Some other examples of conventional circuits are: U.S. Pat. No. 6,873,322; U.S. Pat. No. 6,933,772 U.S. Pat. No. 7,148,666 U.S. Pat. No. 7,282,895; Sahu et al., “A Low Voltage, Dynamic, Noninverting, Synchronous Buck-Boost Converter for Portable Applications,” IEEE Trans. on Power Electronics, Vol. 19, No. 2, March 2004, pp. 443-452; and Lin et al., “Low-Dropout Regulators With Adaptive Reference Control and Dynamic Push-Pull Techniques for Enhancing Transient Performance,” IEEE Trans. on Power Electronics, Vol. 24, No. 4, April 2009, pp. 1016-1022.